interface sensor_if (
        input logic clk,
        input logic rst_n
    );

    /* **** Signals **** */ 
    logic [7:0] data;
    logic       valid;
    /* **** Signals **** */ 

    
    /* **** Modports **** */ 
    // 从 Master 模块的角度看
    modport master (
        output data,
        output valid,
        input  clk,
        input  rst_n
    );
    // 从 Slave 模块的角度看
    modport slave (
        input  clk,
        input  rst_n,
        input  data,
        input  valid
    );
    // 从 Monitor/Testbench 的角度看
    modport monitor (
        input clk,
        input rst_n,
        input data,
        input valid
    );
    /* **** Modports **** */ 
endinterface

module master(sensor_if bus);
    logic [7:0] counter;
    always @(posedge bus.clk) begin
        if (!bus.rst_n) begin
            bus.data <= 8'h00;
            bus.valid <= 1'b0;
            counter <= 8'h00;
        end 
        else begin
            if (counter == 10) begin
                bus.data <= $urandom_range(0, 255);
                bus.valid <= 1'b1;
                counter <= 0;
            end
            else begin
                bus.valid <= 1'b0;
                counter <= counter + 1;
            end
        end
    end

endmodule

module slave(sensor_if bus);
    logic [7:0] recv_data;
    always @(posedge bus.clk) begin
        if (!bus.rst_n) begin
            // reset
        end 
        else begin
            if (bus.valid) begin
                // 处理数据
                recv_data <= bus.data;
                $display("@%g Slave received data: %0d", $time, recv_data);
            end
            else begin
                // 没有数据可用
            end
        end
    end
endmodule

module monitor(sensor_if bus);
    initial begin
        $monitor(
            "At time %0t, data: %0d, valid: %0b",
            $time, bus.data, bus.valid
        );
    end
endmodule

module sensor_tb;
    logic clk;
    logic rst_n;
    sensor_if bus(clk, rst_n);
    
    initial begin
        clk = 0;
        forever #1 clk = ~clk;
    end

    initial begin
        rst_n = 0;
        #5 rst_n = 1; // Release reset after 20 ns
    end

    initial begin
        #100 $finish; // Finish simulation after 100 ns
    end

    master m(bus);
    slave s(bus);
    monitor mon(bus);
endmodule
